`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:13:13 10/24/2012 
// Design Name: 
// Module Name:    MEM_CTR 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MEM_RD_DUAL #(parameter LOG_DEPTH=9, DEPTH=416, LOG_CYCLE=8, CYCLE=160, WIDTH=16, OFFSET=0, GAP=256)
(
	 input clk,
	 input rst,
	 input signed [WIDTH-1:0] ch1_to_rd_r,
	 input signed [WIDTH-1:0] ch1_to_rd_i,
	 input signed [WIDTH-1:0] ch2_to_rd_r,
	 input signed [WIDTH-1:0] ch2_to_rd_i,
	 input [LOG_DEPTH-1:0] addr_wr,
	 output signed [WIDTH-1:0] ch1_rd_r,
    output signed [WIDTH-1:0] ch1_rd_i,
	 output signed [WIDTH-1:0] ch2_rd_r,
    output signed [WIDTH-1:0] ch2_rd_i,
	 output reg[LOG_DEPTH-1:0] addr_rd_ch1,
	 output reg[LOG_DEPTH-1:0] addr_rd_ch2
	 
    );

	reg[LOG_DEPTH-1:0] count;
	
	
	assign ch1_rd_r = ch1_to_rd_r;
	assign ch1_rd_i = ch1_to_rd_i;
	assign ch2_rd_r = ch2_to_rd_r;
	assign ch2_rd_i = ch2_to_rd_i;
	
	
	always@(posedge clk or negedge rst)
	if(!rst)
		count <= 0;
	else if(count == CYCLE-1)
		count <= 0;
	else
		count <= count + 1;
		
	
	always@(posedge clk or negedge rst)
	if(!rst)
	begin
		addr_rd_ch1 <= 0;
		addr_rd_ch2 <= 0;
	end
	else if(addr_wr+count > DEPTH-1)
	begin
		addr_rd_ch1 <= addr_wr + count - DEPTH;
		addr_rd_ch2 <= addr_wr + count + GAP - DEPTH;
	end
	else if(addr_wr+count+GAP > DEPTH-1)
	begin
		addr_rd_ch1 <= addr_wr + count;
		addr_rd_ch2 <= addr_wr + count + GAP - DEPTH;
	end
	else
	begin
		addr_rd_ch1 <= addr_wr + count;
		addr_rd_ch2 <= addr_wr + count + GAP;
	end
	
	
	
endmodule